The UCIe™ (Universal Chiplet Interconnect Express™) 2.0 Specification was released in August 2024, adding support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets – from sort to management in the field.

The webinar explores the new features in the UCIe 2.0 specification including support for 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. The webinar also introduces optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions. It also enables vendor agnostic chiplet interoperability across a flexible and unified approach to SIP management and DFx operations.

Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and coGM Memory and I/O Technologies, Intel Corporation