Stream starts at 7July2024 at 5pm GMT.

The 6502 is a CISC 8 bit CPU. We'll be implementing it as a synchronous bus FPGA module. In this session the internal architecture is (hopefully) finished or almost finished, and all that's left is to write the microcode that implements the actual opcodes.

We'll continue implementing opcodes in the order in which the test program uses them, though we've skipped a few opcodes implemented offline to get to the interesting parts.
Next up is a region implementing the same opcode with all of its different addressing modes.

I'd like to thank my Patreon BBC Micro level supporter, Yehuda T. Deutsch.
You, too, can support my work on Patreon:   / compusar  

Discord server invite:   / discord  

Code written during the stream is available at https://github.com/CompuSAR/sar6502sync
6502 block diagram is at https://www.witwright.com/DonPub/6502...
visual6502 site: https://visual6502.org
WDC datasheet: https://www.westerndesigncenter.com/w...